Enhancing Iterative Layering with SAT Solvers

Iterative Layering is an existing pre-synthesis technique that can be used for constructing a near-optimal representation of the input circuit. Originally, the Iterative Layering algorithm uses SAT instances extensively. However, in the original implementation, they are solved either by exhaustive enumeration of all possible assignments of input variables, or by using BDDs. Both approaches perform poorly, which constrains the size of the circuits that can be processed. In this paper, we propose a new implementation of the algorithm in which all SAT problems are reformulated and solved by a modern SAT solver. Moreover, we use the unsatisfiability proofs produced by the SAT solver and Craig interpolants to fundamentally change the way Iterative Layering handles circuit reconstruction. As a result, our enhanced Iterative Layering promises to scale to larger circuits than the original one. Unfortunately, this preliminary work still does not show evidence of superior overall runtime; accordingly, some parts of the current heuristic will need to be reviewed in future work.